74LV165资料

2022-07-17 来源：趣尚旅游网

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元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification8-bit parallel-in/serial-out shift register74LV165FEATURESDESCRIPTION•Wide operating voltage: 1.0 to 5.5 VThe 74LV165 is a low-voltage Si-gate CMOS device and is pin and•function compatible with 74HC/HCT165.Optimized for low voltage applications: 1.0 to 3.6 V•The 74LV165 is an 8-bit parallel-load or serial-in shift register withAccepts TTL input levels between VCC = 2.7 V and VCC = 3.6 Vcomplementary serial outputs (Q7 and Q7) available from the last•Typical Vstage. When the parallel load (PL) input is LOW, parallel data from theOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, DT0 to D7 inputs are loaded into the register asynchronously. When PLamb = 25°Cis HIGH, data enters the register serially at the DS input and shifts one•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, place to the right (Q0→Q1→Q2, etc.) with each positive-going clockTtransition. This feature allows parallel-to-serial converter expansion byamb = 25°C•tying the Q7 output to the DS input of the succeeding stage.Asynchronous 8-bit parallel loadThe clock input is a gated-OR structure which allows one input to be•Synchronous serial inputused as an active LOW clock enable (CE) input. The pin assignment•for the CP and CE inputs is arbitrary and can be reversed for layoutOutput capability: standardconvenience. The LOW-to-HIGH transition of input CE should only•Itake place while CP HIGH for predictable operation. Either the CP orCC category: MSIthe CE should be HIGH before the LOW-to-HIGH transition of PL toprevent shifting the data when PL is activated.QUICK REFERENCE DATAGND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 nsSYMBOLPARAMETERCONDITIONSTYPICALUNITPropagation delayCL = 15 pF;tVPHL/tPLHCE, CP to Q7, QPL to Q7CC = 3.3 V1818nsD7, Q77 to Q7, Q714fmaxMaximum clock frequency78MHzCIInput capacitance3.5pFCPDPower dissipation capacitance per gateVCC = 3.3 VVI = GND to VCC135pFNOTES:1.CPD is used to determine the dynamic power dissipation (P× VD in µW)PfD = CPD CC2 × fi )ȍ (CL × VCC2 × fo) where:fi = input frequency in MHz; CL = output load capacitance in pF;ȍo = output frequency in MHz; V (C) = sum of the outputs.CC = supply voltage in V;L × VCC2 × foORDERING INFORMATIONPACKAGESTEMPERATURE RANGEOUTSIDE NORTH AMERICANORTH AMERICAPKG. DWG. #16-Pin Plastic DIL–40°C to +125°C74LV165 N74LV165 NSOT38-416-Pin Plastic SO–40°C to +125°C74LV165 D74LV165 DSOT109-116-Pin Plastic SSOP Type II–40°C to +125°C74LV165 DB74LV165 DBSOT338-116-Pin PlasticTSSOP Type I–40°C to +125°C74LV165 PW74LV165PW DHSOT403-1PIN CONFIGURATIONPIN DESCRIPTIONPIN NUMBERSYMBOLFUNCTIONPL116VCCCP2151PLAsynchronous parallel loadCEinput (active LOW)D4314D32CPClock input (LOW toHIGH, edge-triggered)D5413D27Q7Complementary output fromDthe last stage6512D18GNDGround (0 V)D7611D09Q7Serial output from last stageQ7710DS10DSSerial data inputGND89Q711, 12, 13, 14, 3, 4, 5, 6D0 to D7Parallel data inputs15CEClock enable inputSV00585(active LOW)16VCCPositive supply voltage1998 May 072853–1915 19349元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification8-bit parallel-in/serial-out shift register74LV165LOGIC SYMBOLFUNCTIONAL DIAGRAM1011121314345611DD0SD0D1D2D3D4D5D6D712D113D21PL14D33D44D55D6Q7910DS6D7Q77Q791PL2CP8–BIT SHIFT REGISTERCPCEPARALLEL– IN / SERIAL – OUTQ7715CE215SV00586SV00588LOGIC SYMBOL (IEEE/IEC)1SRG8C2 [LOAD]G1 [SHIFT]15>121C3/10113D122D132D14345697SV00587LOGIC DIAGRAMD0D1D2D3D4D5D6D7DSCPSSSSSSDDQDDQDDQDDSQDDQDDQDDSQDDQQ7CECPCPCPCPCPCPCPCPPLFF0FF1FF2FF3FF4FF5FF6FF7Q7RDRDRDRDRDRDRDRDQSV005891998 May 073元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification8-bit parallel-in/serial-out shift register74LV165FUNCTION TABLEOPERATINGOPERATING MODESMODESINPUTSQn REGISTERSOUTPUTSPLCECPDSD0–D7Q0Q1–Q6Q7Q7ParallelParallel loadloadLXXXLLL–LLHLXXXHHH–HHLSerialSerial ShiftShiftHL↑lXLq0–q5q6q6HL↑hXHq0–q5q6q6Hold “do nothing”HHXXXq0q1–q6q7q7NOTES:H=HIGH voltage levelh=HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transitionL=LOW voltage levelI=LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transitionq=lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transitionX=don’t care↑=LOW-to-HIGH clock transitionRECOMMENDED OPERATING CONDITIONSSYMBOLPARAMETERCONDITIONSMINTYPMAXUNITVCCDC supply voltageSee Note 11.03.35.5VVIInput voltage0–VCCVVOOutput voltage0–VCCVTambOperating ambient temperature range in free airSee DC and AC–40+85characteristics–40+125°CVCC = 1.0V to 2.0V––500tr, tfInput rise and fall timesV––200VCC = 2.0V to 2.7V––100ns/VVCC = 2.7V to 3.6VCC = 3.6V to 5.5V––50NOTE:1.The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).SYMBOLPARAMETERCONDITIONSRATINGUNITVCCDC supply voltage–0.5 to +7.0V\"IIKDC input diode currentVI < –0.5 or VI > VCC + 0.5V20mA\"IOKDC output diode currentVO < –0.5 or VO > VCC + 0.5V50mA\"IODC output source or sink current– standard outputs–0.5V < VO < VCC + 0.5V25mA\"IGND,DC VCC or GND current for types with\"ICC– standard outputs50mATstgStorage temperature range–65 to +150°CPower dissipation per packagefor temperature range: –40 to +125°CPTOT– plastic DILabove +70°C derate linearly with 12 mW/K750– plastic mini-pack (SO)above +70°C derate linearly with 8 mW/K500mW– plastic shrink mini-pack (SSOP and TSSOP)above +60°C derate linearly with 5.5 mW/K400NOTES:1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of thedevice at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.1998 May 074元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification8-bit parallel-in/serial-out shift register74LV165DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltages are referenced to GND (ground = 0 V).LIMITSSYMBOLPARAMETERTEST CONDITIONS-40°C to +85°C -40°C to +125°CUNITMINTYP1MAXMINMAXVCC = 1.2 V0.90.9VCC = 2.0 V1.41.4IHHIGH level InputVvoltageVCC = 2.7 to 3.6 V2.02.0VVCC = 4.5 to 5.5 V0.7Philips Semiconductors

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